The Design and Implementation of An IP Bus Bridge


What a computer can do is limited by its hardware. The hardware configuration of a computer is statically determined by the physical attachment of devices, such as CPUs, memories and expansion peripherals. Device connections are done using a bus, but buses are limited in distance, number of devices and concurrent transactions, and reconfigurability. Even specialized I/O networks only partially eliminate these problems. However, the hardware resources required by applications vary. Improved flexibility in dynamic system configuration is necessary.

This thesis proposes the most flexible and scalable alternative possible: using an IP-level network as the interconnect for both memory and I/O devices. An IP network can improve flexibility, cost and scalability.

A bus bridge that provides protocol translation between the computer bus and Internet Protocol has been designed, implemented, and evaluated. The IP Bus Bridge connects the memory and peripherals of a MIPS-based system over Ethernet, with or without IP. The performance of the system with and without cache is evaluated for latencies up to 200 msec, demonstrating that it is possible to connect memory via IP.




特別に設計されたI/O ネットワークでさえ、それら制限の一部分を解決するにすぎない。

この問題を解決するために、本論文ではIP レベルネットワークをメモリとI/O デバイスのバス相互接続に用いる手法を提案する。

そして提案内容の一部を実現するために、バスのプロトコルとインターネットプロトコルとを相互に変換するIP バスブリッジを設計し、実装、評価した。

IP バスブリッジはMIPS アーキテクチャ CPU とメモリと拡張機器をEthernet によって接続しており、IP を使用した接続と使用しない接続の両方に対応している。


その結果メモリとCPU をIP によって接続し、演算ができることを確認した。

Full Paper

Full paper in PDF (in Japanese)

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